There are four biasing methods for MOSFET: –
1- Drain to gate bias
2-Voltage divider bias
3-Fixed bias
4- Self bias
Drain to gate bias configuration
![](https://i0.wp.com/tech-notes.quantmasters.in/wp-content/uploads/2022/10/image-22.png?resize=580%2C243&ssl=1)
- DC Analysis-
- Gate current , IG =0
- So, we have voltage drop across resistance RG = VRG = 0
- Therefore, we get a direct connection between drain and source i.e.
- VD = VG
- So VDS = VGS
- Drain to gate bias always enables MOSFET in saturation region
- For output circuit, we have: VDS = VDD – IDRD
Voltage divider bias configuration:
![](https://i0.wp.com/tech-notes.quantmasters.in/wp-content/uploads/2022/10/image-23.png?resize=349%2C394&ssl=1)
![](https://i0.wp.com/tech-notes.quantmasters.in/wp-content/uploads/2022/10/image-24.png?resize=305%2C324&ssl=1)
DC – ANALYSIS:
Using voltage divider, gate voltage is obtained by:
![](https://i0.wp.com/tech-notes.quantmasters.in/wp-content/uploads/2022/10/image-25.png?resize=356%2C75&ssl=1)
Applying KVL is loop 1, we get
VG – VGS – IDRS = 0
VGS = VG – IDRS …. (1)
Assume that MOSFET is in saturation, so we have ID = Kn (VGS– VTN)2
By solving the quadratic equation, determine the value of VGSor ID, then apply KVL in
source to drain loop
VDD – IDRD – VDS – ISRS = 0
VDS = VDD – ID (RS + RD)
If VDS> VGS –VTN, then the transistor is indeed biased in saturation region, as we have assumed.
However, if VDS < VDS (sat), then transistor is biased in the non saturation region
Therefore from equation (1):
VGS = VG – IDRS
![](https://i0.wp.com/tech-notes.quantmasters.in/wp-content/uploads/2022/10/image-26.png?resize=229%2C157&ssl=1)
Fixed bias configuration
![](https://i0.wp.com/tech-notes.quantmasters.in/wp-content/uploads/2022/10/image-27.png?resize=580%2C264&ssl=1)
DRAWBACK OF FIXED BIAS:
It is a dual battery design which makes it expensive and more space occupied bias Configuration
Self bias configuration:
![](https://i0.wp.com/tech-notes.quantmasters.in/wp-content/uploads/2022/10/image-28.png?resize=580%2C294&ssl=1)
DC ANALYSIS:
0 = VGS + IDRS
VGS = – IDRS
(ID)Q=-(VGS)Q
![](https://i0.wp.com/tech-notes.quantmasters.in/wp-content/uploads/2022/10/image-29.png?resize=580%2C432&ssl=1)
For dc analysis, we draw the circuit as:
![](https://i0.wp.com/tech-notes.quantmasters.in/wp-content/uploads/2022/10/image-30.png?resize=580%2C599&ssl=1)
So, the source voltage is
VS = VG – VGS
Assume that transistor is in saturation. So, we have
![](https://i0.wp.com/tech-notes.quantmasters.in/wp-content/uploads/2022/10/image-31.png?resize=580%2C326&ssl=1)