Field-Effect Transistors(FET)

The primary difference between the two different types of transistors is the fact that:
- The BJT transistor is a current-controlled device
- whereas the JFET transistor is a voltage-controlled device

For the FET an electric field is established by the charges present, which controls the conduction path of the output circuit without the need for direct contact between the controlling and controlled quantities.
The JFET is abbreviated as Junction Field Effect Transistor.
The types of JFET are n-channel FET and P-channel FET.
A p-type material is added to the n-type substrate in n-channel FET, whereas an n-type material is added to the ptype substrate in p-channel FET.
Hence it is enough to discuss one type of FET to understand both.

N-Channel FET

The N-channel FET is the mostly used Field Effect Transistor.
For the fabrication of N channel FET, a narrow bar of N-type semiconductor is taken on which P-type material is formed by diffusion on the opposite sides.
These two sides are joined to draw a single connection for gate terminal. This can be understood from the following figure.

These two gate depositions p−type materials form two PN diodes.
The area between gates is called as a channel.
The majority carriers pass through this channel.
Hence the cross sectional form of the FET is understood as the following figure.

Ohmic contacts are made at the two ends of the n-type semiconductor bar, which form the source and the drain.
The source and the drain terminals may be interchanged.

Operation of N-channel FET

Before going into the operation of the FET one should understand how the depletion layers are formed.
For this, let us suppose that the voltage at gate terminal say V_GG is reverse biased while the voltage at drain terminal say V_DD is not applied. Let this be the case 1.

In case 1, When V_GG is reverse biased and V_DD is not applied, the depletion regions between P and N layers tend to expand. This happens as the negative voltage applied, attracts the holes from the p-type layer towards the gate terminal.
In case 2, When V_DD is applied positive terminal to drain and negative terminal to source positive terminal to drain and negative terminal to source and V_GG is not applied, the electrons flow from source to drain which constitute the drain current I_D.

Let us now consider the following figure, to understand what happens when both the supplies are given.

The supply at gate terminal makes the depletion layer grow and the voltage at drain terminal allows the drain current from source to drain terminal.
Suppose the point at source terminal is B and the point at drain terminal is A, then the resistance of the channel will be such that the voltage drop at the terminal A is greater than the voltage drop at the terminal B.
Which means, V_A>V_B
Hence the voltage drop is being progressive through the length of the channel.
So, the reverse biasing effect is stronger at drain terminal than at the source terminal.
This is why the depletion layer tends to penetrate more into the channel at point A than at point B, when both V_GG and V_DD are applied.
The following figure explains this.

Depletion Mode of Operation

As the width of depletion layer plays an important role in the operation of FET, the name depletion mode of operation implies.
We have another mode called enhancement mode of operation, which will be discussed in the operation of MOSFETs.
But JFETs have only depletion mode of operation.
Let us consider that there is no potential applied between gate and source terminals and a potential V_DD is applied between drain and source.
Now, a current I_D flows from drain to source terminal, at its maximum as the channel width is more.
Let the voltage applied between gate and source terminal V_GG is reverse biased.
This increases the depletion width, as discussed above.
As the layers grow, the cross-section of the channel decreases and hence the drain current I_D also decreases.
When this drain current is further increased, a stage occurs where both the depletion layers touch each other, and prevent the current I_D flow.
This is clearly shown in the following figure.

The voltage at which both these depletion layers literally “touch” is called as “Pinch off voltage”. It is indicated as V_P.
The drain current is literally nil at this point.
Hence the drain current is a function of reverse bias voltage at gate.
Since gate voltage controls the drain current, FET is called as the voltage controlled device.
This is more clearly understood from the drain characteristics curve.

Drain Characteristics of JFET

Let us try to summarize the function of FET through which we can obtain the characteristic curve for drain of FET.
The circuit of FET to obtain these characteristics is given below.

When the voltage between gate and source V_GS is zero, or they are shorted, the current I_D from source to drain is also nil as there is no V_DS applied.
As the voltage between drain and source V_DS is increased, the current flow I_D from source to drain increases.
This increase in current is linear up to a certain point A, known as Knee Voltage.
The gate terminals will be under reverse biased condition and as I_D increases, the depletion regions tend to constrict.
This constriction is unequal in length making these regions come closer at drain and farther at drain, which leads to pinch off voltage.
The pinch off voltage is defined as the minimum drain to source voltage where the drain current approaches a constant saturation value.
The point at which this pinch off voltage occurs is called as Pinch off point, denoted as B.
As V_DS is further increased, the channel resistance also increases in such a way that I_D practically remains constant.
The region BC is known as saturation region or amplifier region.
All these along with the points A, B and C are plotted in the graph below.

The drain characteristics are plotted for drain current I_D against drain source voltage V_DS for different values of gate source voltage VGS.
The overall drain characteristics for such various input voltages is as given under.

As the negative gate voltage controls the drain current, FET is called as a Voltage controlled device.
The drain characteristics indicate the performance of a FET.
The drain characteristics plotted above are used to obtain the values of Drain resistance, Transconductance and Amplification Factor.

P-Channel FET

The p -channel JFET is constructed in exactly the same manner as the n -channel device but with a reversal of the p – and n -type materials.
The defined current directions are reversed, as are the actual polarities for the voltages V_GS and V_DS .
For the p -channel device, the channel will be constricted by increasing positive voltages from gate to source and the double-subscript notation for V_DS will result in negative voltages for V_DS on the characteristics.
Do not let the minus signs for V_DS confuse you.
They simply indicate that the source is at a higher potential than the drain.

MOSFET

FETs have a few disadvantages like high drain resistance, moderate input impedance and slower operation.
To overcome these disadvantages, the MOSFET which is an advanced FET is invented.
MOSFET stands for Metal Oxide Silicon Field Effect Transistor or Metal Oxide Semiconductor Field Effect Transistor.
This is also called as IGFET meaning Insulated Gate Field Effect Transistor.
The FET is operated in both depletion and enhancement modes of operation.
The following figure shows how a practical MOSFET looks like.

Construction of a MOSFET

The construction of a MOSFET is a bit similar to the FET.
An oxide layer is deposited on the substrate to which the gate terminal is connected.
This oxide layer acts as an insulator (sio₂ insulates from the substrate), and hence the MOSFET has another name as IGFET.
In the construction of MOSFET, a lightly doped substrate, is diffused with a heavily doped region.
Depending upon the substrate used, they are called as P-type and N-type MOSFETs.
The following figure shows the construction of a MOSFET.

The voltage at gate controls the operation of the MOSFET.
In this case, both positive and negative voltages can be applied on the gate as it is insulated from the channel.
With negative gate bias voltage, it acts as depletion MOSFET while with positive gate bias voltage it acts as an Enhancement MOSFET.

Classification of MOSFETs

Depending upon the type of materials used in the construction, and the type of operation, the MOSFETs are classified as in the following figure.

The N-channel MOSFETs are simply called as NMOS.
The symbols for N-channel MOSFET are as given below.

The P-channel MOSFETs are simply called as PMOS.
The symbols for P-channel MOSFET are as given below:

Construction of N- Channel MOSFET

A lightly doped P-type substrate is taken into which two heavily doped N-type regions are diffused, which act as source and drain.
Between these two N+ regions, there occurs diffusion to form an N-channel, connecting drain and source.
A thin layer of Silicon dioxide (SiO₂) is grown over the entire surface and holes are made to draw ohmic contacts for drain and source terminals.
A conducting layer of aluminum is laid over the entire channel, upon this SiO₂ layer from source to drain which constitutes the gate.
The SiO₂ substrate is connected to the common or ground terminals.

Because of its construction, the MOSFET has a very less chip area than BJT, which is 5% of the occupancy when compared to bipolar junction transistor.
This device can be operated in modes which are depletion and enhancement modes.

Working of N – Channel depletion mode MOSFET

The diffused channel N between two N+ regions, the insulating dielectric SiO₂ and the aluminum metal layer of the gate together form a parallel plate capacitor.
If the NMOS has to be worked in depletion mode, the gate terminal should be at negative potential while drain is at positive potential, as shown in the following figure.

When no voltage is applied between gate and source, some current flows due to the voltage between drain and source.
Let some negative voltage is applied at V_GG.
Then the minority carriers i.e. holes, get attracted and settle near SiO₂ layer.
But the majority carriers, i.e., electrons get repelled.
With some amount of negative potential at V_GG a certain amount of drain current I_D flows through source to drain.
When this negative potential is further increased, the electrons get depleted and the current I_D decreases.
Hence the more negative the applied V_GG, the lesser the value of drain current I_D will be.
The channel nearer to drain gets more depleted than at source like in FET and the current flow decreases due to this effect.
Hence it is called as depletion mode MOSFET.

Working of N-Channel MOSFET Enhancement Mode

If we can change the polarities of the voltage V_GG, the same MOSFET can be worked in enhancement mode.
So, let us consider the MOSFET with gate source voltage V_GG being positive as shown in the following figure.

When no voltage is applied between gate and source, some current flows due to the voltage between drain and source.
Let some positive voltage is applied at V_GG.
Then the minority carriers i.e. holes, get repelled and the majority carriers i.e. electrons gets attracted towards the SiO₂ layer.
With some amount of positive potential at V_GG a certain amount of drain current I_D flows through source to drain.
When this positive potential is further increased, current I_D increases due to the flow of electrons from source and these are pushed further due to the voltage applied at V_GG.
Hence the more positive the applied V_GG, the more the value of drain current I_D will be.
The current flow gets enhanced due to the increase in electron flow better than in depletion mode.
Hence this mode is termed as Enhanced Mode MOSFET.

P – Channel MOSFET

The construction and working of a PMOS is same as NMOS.
A lightly doped n-substrate is taken into which two heavily doped P+ regions are diffused.
These two P+ regions act as source and drain.
A thin layer of SiO₂ is grown over the surface.
Holes are cut through this layer to make contacts with P+ regions, as shown in the following figure.

Working of PMOS

When the gate terminal is given a negative potential at V_GG than the drain source voltage V_DD, then due to the P+ regions present, the hole current is increased through the diffused P channel and the PMOS works in Enhancement Mode.
When the gate terminal is given a positive potential at V_GG than the drain source voltage V_DD, then due to the repulsion, the depletion occurs due to which the flow of current reduces. Thus PMOS works in Depletion Mode.
Though the construction differs, the working is similar in both the type of MOSFETs.
Hence with the change in voltage polarity both of the types can be used in both the modes.
This can be better understood by having an idea on the drain characteristics curve.

Drain Characteristics

The drain characteristics of a MOSFET are drawn between the drain current I_D and the drain source voltage V_DS.
The characteristic curve is as shown below for different values of inputs.

Actually when V_DS is increased, the drain current I_D should increase, but due to the applied V_GS, the drain current is controlled at certain level.
Hence the gate current controls the output drain current.

Transfer Characteristics

Transfer characteristics define the change in the value of V_DS with the change in I_D and V_GS in both depletion and enhancement modes.
The below transfer characteristic curve is drawn for drain current versus gate to source voltage.

The transfer characteristics defined by Shockley’s equation are unaffected by the network in which the device is employed.

I_D=I_DSS(1-(V_GS/V_p))²

ENHANCEMENT-TYPE MOSFET

Although there are some similarities in construction and mode of operation between depletion type and enhancement-type MOSFETs, the characteristics of the enhancement-type MOSFET are quite different from anything obtained thus far.
The transfer curve is not defined by Shockley’s equation, and the drain current is now cut off until the gate-to-source voltage reaches a specific magnitude.
In particular, current control in an n -channel device is now effected by a positive gate-to-source voltage rather than the range of negative voltages encountered for n -channel JFETs and n -channel depletion-type MOSFETs.

Basic Construction

A slab of p -type material is formed from a silicon base and is again referred to as the substrate.
As with the depletion-type MOSFET, the substrate is sometimes internally connected to the source terminal, whereas in other cases a fourth lead (labeled SS) is made available for external control of its potential level.
The source and drain terminals are again connected through metallic contacts to n -doped regions, but note the absence of a channel between the two n -doped regions.

This is the primary difference between the construction of depletion-type and enhancement-type MOSFETs—the absence of a channel as a constructed component of the device.
The SiO 2 layer is still present to isolate the gate metallic platform from the region between the drain and source, but now it is simply separated from a section of the p -type material.
In summary, therefore, the construction of an enhancement-type MOSFET is quite similar to that of the depletion-type MOSFET, except for the absence of a channel between the drain and source terminals.

Basic Operation and Characteristics

If V_GS is set at 0 V and a voltage applied between the drain and the source of the device, the absence of an n -channel (with its generous number of free carriers) will result in a current of effectively 0 A.

It is not sufficient to have a large accumulation of carriers (electrons) at the drain and the source (due to the n -doped regions) if a path fails to exist between the two.
With V_DS some positive voltage, V_GS at 0 V, and terminal SS directly connected to the source, there are in fact two reverse-biased p – n junctions between the n -doped regions and the p -substrate to oppose any significant flow between drain and source.

If both V_DS and V_GS have been set at some positive voltage greater than 0 V, establishing the drain and the gate at a positive potential with respect to the source.
The positive potential at the gate will pressure the holes (since like charges repel) in the p -substrate along the edge of the SiO₂ layer to leave the area and enter deeper regions of the p -substrate.
The result is a depletion region near the SiO₂ insulating layer void of holes.
However, the electrons in the p -substrate (the minority carriers
of the material) will be attracted to the positive gate and accumulate in the region near the surface of the SiO₂ layer.
The SiO₂ layer and its insulating qualities will prevent the negative carriers from being absorbed at the gate terminal.
As V_GS increases in magnitude, the concentration of electrons near the SiO₂ surface increases until eventually the induced n -type region can support a measurable flow between drain and source.
The level of V_GS that results in the significant increase in drain current is called the threshold voltage and is given the symbol V_T .
Since the channel is nonexistent with V_GS = 0 V and “enhanced” by the application of a positive gate-to-source voltage, this type of MOSFET is called an enhancement-type MOSFET.
Both depletion- and enhancement type MOSFETs have enhancement-type regions, but the label was applied to the latter since it is its only mode of operation.
As V_GS is increased beyond the threshold level, the density of free carriers in the induced channel will increase, resulting in an increased level of drain current.
However, if we hold V_GSconstant and increase the level of V_DS , the drain current will eventually reach a saturation level as occurred for the JFET and depletion-type MOSFET.
The leveling off of I_D is due to a pinching-off process depicted by the narrower channel at the drain end of the induced channel.

For levels of V_GS > V_T, the drain current is related to the applied gate-to-source voltage by the following nonlinear relationship:
I_D = k(V_GS – V_T)²

p -Channel Enhancement-Type MOSFETs

The construction of a p -channel enhancement-type MOSFET is exactly the reverse of that in n -channel enhancement-type MOSFET.
That is, there is now an n -type substrate and p -doped regions under the drain and source connections.
The terminals remain as identified, but all the voltage polarities and the current directions are reversed.
The drain characteristics will appear as shown in Fig. , with increasing levels of current resulting from increasingly negative values of V_GS.