MOSFET Biasing

There are four biasing methods for MOSFET: –

1- Drain to gate bias

2-Voltage divider bias

3-Fixed bias

4- Self bias

Drain to gate bias configuration

  • DC Analysis-
  • Gate current , IG =0
  • So, we have voltage drop across resistance RG = VRG = 0
  • Therefore, we get a direct connection between drain and source i.e.
  • VD = VG
  • So VDS = VGS
  • Drain to gate bias always enables MOSFET in saturation region
  • For output circuit, we have: VDS = VDD – IDRD

Voltage divider bias configuration:

DC – ANALYSIS:

Using voltage divider, gate voltage is obtained by:

Applying KVL is loop 1, we get

VG – VGS – IDRS = 0

VGS = VG – IDRS …. (1)

Assume that MOSFET is in saturation, so we have ID = Kn (VGS– VTN)2

By solving the quadratic equation, determine the value of VGSor ID, then apply KVL in

source to drain loop

VDD – IDRD – VDS – ISRS = 0

VDS = VDD – ID (RS + RD)

If VDS> VGS –VTN, then the transistor is indeed biased in saturation region, as we have assumed.

However, if VDS < VDS (sat), then transistor is biased in the non saturation region

Therefore from equation (1):

VGS = VG – IDRS

Fixed bias configuration

DRAWBACK OF FIXED BIAS:
It is a dual battery design which makes it expensive and more space occupied bias Configuration

Self bias configuration:

DC ANALYSIS:
0 = VGS + IDRS
VGS = – IDRS

(ID)Q=-(VGS)Q

For dc analysis, we draw the circuit as:

So, the source voltage is
VS = VG – VGS
Assume that transistor is in saturation. So, we have

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